The proposed algorithm is suitable for BeiDou weak signal bit synchronization with large frequency deviation. To confirm the feasibility of the proposed algorithm, real data tests are conducted. This algorithm can remove the effect of BeiDou NH code effectively and weaken the influence of frequency deviation. The results show that the proposed algorithm outperforms the traditional method with a frequency deviation of 50 Hz. Finally, Monte Carlo simulations are conducted to analyze the detection performance of the proposed algorithm compared with a traditional algorithm under the CN0s of 20~40 dB-Hz and different frequency deviations. Secondly, the maximum likelihood function detection is used to improve the detection probability of weak signals. Firstly, a differential coherent approach is used to remove the effect of frequency deviation, and the differential delay time is set to be a multiple of bit cycle to remove the influence of NH code. In order to realize bit synchronization for BeiDou weak signals with large frequency deviation, a bit synchronization algorithm based on differential coherent and maximum likelihood is proposed. Therefore, a bit synchronization algorithm is necessary to obtain bit edges and NH code phases. Han, Zhifeng Liu, Jianye Li, Rongbing Zeng, Qinghua Wang, YiīeiDou system navigation messages are modulated with a secondary NH (Neumann-Hoffman) code of 1 kbps, where frequent bit transitions limit the coherent integration time to 1 millisecond. (semiconductor integrated circuits)Ī Modified Differential Coherent Bit Synchronization Algorithm for BeiDou Weak Signals with Large Frequency Deviation. With a 4.9 MHz sine wave input, the prototype ADC implemented in a 0.18-, demonstrates a maximum signal-to-noise distortion ratio (SNDR) and SFDR of 66.32 and 83.38 dB, respectively, at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply. This paper describes a 12- bit 40 MS/s calibration-free pipelined analog-to-digital converter (ADC), which is optimized for high spurious free dynamic range (SFDR) performance and low power dissipation. Wei Qi Yin Xiumei Han Dandan Yang Huazhong, E-mail: [Department of Electronic Engineering, Tsinghua University, Beijing 100084 (China) A 12- bit 40 MS/s pipelined ADC with over 80 dB SFDRĮnergy Technology Data Exchange (ETDEWEB)

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